View MODEL1_7342615.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

low power, low noise and distortion, rail-to-rail output amplifiers ada4841-1/ada4841-2 rev. e information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2005C2010 analog devices, inc. all rights reserved. features low power: 1.1 ma/amp low wideband noise 2.1 nv/hz 1.4 pa/hz low 1/f noise 7 nv/hz @ 10 hz 13 pa/hz @ 10 hz low distortion: ?105 dbc @ 100 khz, v o = 2 v p-p high speed 80 mhz, ?3 db bandwidth (g = +1) 12 v/s slew rate 175 ns settling time to 0.1% low offset voltage: 0.3 mv maximum rail-to-rail output power down wide supply range: 2.7 v to 12 v applications low power, low noise signal processing battery-powered instrumentation 16-bit pulsar? adc drivers connection diagrams v out 3 4 6 5 27 18 ?v s ?in +in +v s nc nc power down 05614-001 ada4841-1 top view (not to scale) figure 1. 8-lead soic (r) v out 1 ?v s 2 +in 3 +v s 6 power down 5 ?in 4 ada4841-1 05614-099 figure 2. 6-lead sot-23 (rj) out1 1 ? in1 2 +in1 3 ? v s 4 +v s 8 out2 7 ? in2 6 +in2 5 ada4841-2 top view (not to scale) 05614-064 notes 1. for 8-lead lfcsp_wd, connect exposed paddle to gnd. figure 3. 8-lead msop (rm), 8-lead soic_n (r), and 8-lead lfcsp_wd (cp) general description the ada4841-1/ada4841-2 are unity gain stable, low noise and distortion, rail-to-rail output amplifiers that have a quiescent current of 1.5 ma maximum. in spite of their low power consumption, these amplifiers offer low wideband voltage noise performance of 2.1 nv/ hz and 1.4 pa/ hz current noise, along with excellent spurious-free dynamic range (sfdr) of ?105 dbc at 100 khz. to maintain a low noise environment at lower frequencies, the amplifiers have low 1/f noise of 7 nv/ hz and 13 pa/ hz at 10 hz. the ada4841-1/ada4841-2 output can swing to less than 50 mv of either rail. the input common-mode voltage range extends down to the negative supply. the ada4841-1/ ada4841-2 can drive up to 10 pf of capacitive load with minimal peaking. the ada4841-1/ada4841-2 provide the performance required to efficiently support emerging 16-bit to 18-bit adcs and are ideal for portable instrumentation, high channel count, industrial measurement, and medical applications. the ada4841-1/ ada4841-2 are ideally suited to drive the ad7685 / ad7686, 16-bit pulsar adcs. the ada4841-1/ada4841-2 packages feature rohs compliant lead finishes. the amplifiers are rated to work over the industrial temperature range (?40c to +125c). ? 30 ?120 0.01 1 05614-048 frequency (mhz) harmonic distortion (dbc) 0.1 2v p-p third ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 v s = 5v g = +1 2v p-p second figure 4. harmonic distortion
important links for the ada4841-1_4841-2 * last content update 08/17/2013 01:21 pm documentation an-931: understanding pulsar adc support circuitry an-649: using the analog devices active filter design tool an-581: biasing and decoupling op amps in single supply apps an-402: replacing output clamping op amps with input clamping amps an-417: fast rail-to-rail operational amplifiers ease design constraints in low voltage high speed systems an-202: an ic amplifier users guide to decoupling, grounding, and making things go right for a change mt-060: choosing between voltage feedback and current feedback op amps mt-059: compensating for the effects of input capacitance on vfb and cfb op amps used in current-to-voltage converters mt-058: effects of feedback capacitance on vfb and cfb op amps mt-056: high speed voltage feedback op amps mt-053: op amp distortion: hd, thd, thd + n, imd, sfdr, mtpr mt-052: op amp noise figure: don't be mislead mt-050: op amp total output noise calculations for second-order system mt-049: op amp total output noise calculations for single-pole system mt-048: op amp noise relationships: 1/f noise, rms noise, and equivalent noise bandwidth mt-047: op amp noise mt-033: voltage feedback op amp gain and bandwidth mt-032: ideal voltage feedback (vfb) op amp a stress-free method for choosing high-speed op amps for the ada4841-1: cn-0255 a complete single-supply, 16-bit, 100 ksps pulsar adc system dissipates 8 mw (for the ada4841-1) ug-127: universal evaluation board for high speed op amps in sot-23-5/sot-23-6 packages ug-101: evaluation board user guide for the ada4841-2: ug-129: evaluation board user guide ug-128: universal evaluation board for dual high speed op amps in soic packages design collaboration community collaborate online with the adi support team and other designers about select adi products. follow us on twitter: www.twitter.com/adi_news like us on facebook: www.facebook.com/analogdevicesinc parametric selection tables find similar products by operating parameters high speed amplifiers selection table evaluation kits & symbols & footprints view the evaluation board and kits page for the ada4841-1 view the evaluation board and kits page for the ada4841-2 symbols and footprints for the ada4841-1 symbols and footprints for the ada4841-2 design tools, models, drivers & software dbm/dbu/dbv calculator power dissipation vs die temp adisimopamp? analog filter wizard 2.0 opamp stability ada4841 spice macro model, rev 0, 2/2007 design support submit your support request here: linear and data converters embedded processing and dsp telephone our customer interaction centers toll free: americas: 1-800-262-5643 europe: 00800-266-822-82 china: 4006-100-006 india: 1800-419-0108 russia: 8-800-555-45-90 quality and reliability lead(pb)-free data sample & buy ada4841-1 ada4841-2 view price & packaging request evaluation board request samples check inventory & purchase find local distributors * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page (labeled 'important links') does not constitute a change to the revision number of the product data sheet. this content may be frequently modified. powered by tcpdf (www.tcpdf.org)
ada4841-1/ada4841-2 rev. e | page 2 of 20 table of contents features .............................................................................................. 1 applications....................................................................................... 1 connection diagrams...................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 absolute maximum ratings............................................................ 6 thermal resistance ...................................................................... 6 maximum power dissipation ..................................................... 6 esd caution.................................................................................. 6 typical performance characteristics ............................................. 7 theory of operation ...................................................................... 13 amplifier description................................................................ 13 dc errors .................................................................................... 13 noise considerations ................................................................. 13 headroom considerations........................................................ 14 capacitance drive ...................................................................... 15 input protection ......................................................................... 15 power-down operation ............................................................ 16 applications information .............................................................. 17 typical performance values...................................................... 17 16-bit adc driver..................................................................... 17 reconstruction filter ................................................................. 17 layout considerations............................................................... 18 ground plane.............................................................................. 18 power supply bypassing ............................................................ 18 outline dimensions ....................................................................... 19 ordering guide .......................................................................... 20 revision history 12/10rev. d to rev. e changes to negative power supply rejection ration conditions .. 3 changes to ordering guide .......................................................... 20 1/10rev. c to rev. d added lfcsp package.......................................................universal changes to operating temperature range parameter, table 4.. 6 updated outline dimensions ....................................................... 19 changes to ordering guide .......................................................... 20 3/06rev. b to rev. c added sot-23 package .....................................................universal changes to general description .................................................... 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 changes to table 3............................................................................ 5 changes to input protection section ........................................... 15 changes to ordering guide .......................................................... 20 10/05rev. a to rev. b added ada4841-2.............................................................universal changes to general description and features ............................. 1 changes to table 1............................................................................ 3 changes to table 2............................................................................ 4 changes to table 3............................................................................ 5 changes to table 4, table 5, and figure 4 ..................................... 6 changes to figure 6...........................................................................7 changes to figure 12, figure 13, figure 15, and figure 16..........8 deleted figure 25; renumber sequentially ................................ 10 changes to figure 24 and figure 28............................................. 10 changes to figure 31...................................................................... 11 inserted figure 37; renumber sequentially................................ 12 changes to amplifier description section and figure 39 ........ 13 changed dc performance considerations section to dc errors section...................................................................... 13 changes to noise considerations section .................................. 14 changes to headroom considerations section and figure 39 15 changes to power-down operation section.............................. 16 changes to 16-bit adc driver section, figure 48, and figure 49 ................................................................ 17 changes to power supply bypassing section ............................. 18 updated outline dimensions....................................................... 19 changes to ordering guide .......................................................... 20 9/05rev. 0 to rev. a changes to features ..........................................................................1 changes to figure 2...........................................................................1 changes to figure 12.........................................................................8 changes to figure 40...................................................................... 14 changes to headroom considerations section ......................... 15 7/05revision 0: initial version
ada4841-1/ada4841-2 rev. e | page 3 of 20 specifications t a = 25c, v s = 5 v, r l = 1 k, gain = +1, unless otherwise noted. table 1. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v o = 0.02 v p-p 58 80 mhz v o = 2 v p-p 3 mhz slew rate g = +1, v o = 9 v step, r l = 1 k 12 13 v/s settling time to 0.1% g = +1, v o = 8 v step 650 ns settling time to 0.01% g = +1, v o = 8 v step 1000 ns noise/harmonic performance harmonic distortion hd2/hd3 f c = 100 khz, v o = 2 v p-p, g = +1 ?111/?105 dbc f c = 1 mhz, v o = 2 v p-p ?80/?67 dbc input voltage noise f = 100 khz 2.1 nv/hz input current noise f = 100 khz 1.4 pa/hz dc performance input offset voltage 40 300 v input offset voltage drift 1 v/c input bias current 3 5.3 a input offset current 0.1 0.5 a open-loop gain v o = 4 v 103 120 db input characteristics input resistance, common mode 90 m input resistance, differential mode 25 k input capacitance, common mode 1 pf input capacitance, differential mode 3 pf input common-mode voltage range ?5.1 +4 v common-mode rejection ratio (cmrr) v cm = 4 v 95 115 db matching characteristics (ada4841-2) input offset voltage 70 v input bias current 60 na power down pin (ada4841-1) power down voltage enabled >3.6 v power down voltage power down <3.2 v input current enable power down = +5 v 1 2 a power down power down = ?5 v ?13 ?30 a switching speed enable 1 s power down 40 s output characteristics output voltage swing g > +1 4.9 4.955 v output current limit sourcing, v in = +v s , r l = 50 to gnd 30 ma sinking, v in = ?v s , r l = 50 to gnd 60 ma capacitive load drive 30% overshoot 15 pf power supply operating range 2.7 12 v quiescent current/amplifier power down = +5 v 1.2 1.5 ma power down = ?5 v 40 90 a positive power supply rejection ratio +v s = +5 v to +6 v, ?v s = ?5 v 95 110 db negative power supply rejection ratio +v s = +5 v, ?v s = ?5 v to ?6 v 96 120 db
ada4841-1/ada4841-2 rev. e | page 4 of 20 t a = 25c, v s = 5 v, r l = 1 k, gain = +1, v cm = 2.5 v, unless otherwise noted. table 2. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v o = 0.02 v p-p 54 80 mhz v o = 2 v p-p 3 mhz slew rate g = +1, v o = 4 v step, r l = 1 k 10 12 v/s settling time to 0.1% g = +1, v o = 2 v step 175 ns settling time to 0.01% g = +1, v o = 2 v step 550 ns noise/harmonic performance harmonic distortion hd2/hd3 f c = 100 khz, v o = 2 v p-p ?109/?105 dbc f c = 1 mhz, v o = 2 v p-p ?78/?66 dbc input voltage noise f = 100 khz 2.1 nv/hz input current noise f = 100 khz 1.4 pa/hz crosstalk f = 100 khz ?117 db dc performance input offset voltage 40 300 v input offset voltage drift 1 v/c input bias current 3 5.3 a input offset current 0.1 0.4 a open-loop gain v o = 0.5 v to 4.5 v 103 124 db input characteristics input resistance, common mode 90 m input resistance, differential mode 25 k input capacitance, common mode 1 pf input capacitance, differential mode 3 pf input common-mode voltage range ?0.1 +4 v common-mode rejection ratio (cmrr) v cm = 1.5 v 88 115 db matching characteristics (ada4841-2) input offset voltage 70 v input bias current 70 na power down pin (ada4841-1) power down voltage enabled >3.6 power down voltage power down <3.2 v input current enable power down = 5 v 1 2 a power down power down = 0 v ?13 ?30 a switching speed enable 1 s power down 40 s output characteristics output voltage swing g > +1 0.08 to 4.92 0.029 to 4.974 v output current limit sourcing, v in = +v s , r l = 50 to v cm 30 ma sinking, v in = ?v s , r l = 50 to v cm 60 ma capacitive load drive 30% overshoot 15 pf power supply operating range 2.7 12 v quiescent current/amplifier power down = 5 v 1.1 1.4 ma power down = 0 v 35 70 a positive power supply rejection ratio +v s = +5 v to +6 v, ?v s = 0 v 95 110 db negative power supply rejection ratio +v s = +5 v, ?v s = 0 v to ?1 v 96 120 db
ada4841-1/ada4841-2 rev. e | page 5 of 20 t a = 25c, v s = 3 v, r l = 1 k, gain =+1, v cm = 1.5 v, unless otherwise noted. table 3. parameter conditions min typ max unit dynamic performance ?3 db bandwidth v o = 0.02 v p-p 52 80 mhz slew rate g = +1, v o = 2 v step, r l = 1 k 10 12 v/s settling time to 0.1% g = +1, v o = 1 v step 120 ns settling time to 0.01% g = +1, v o = 1 v step 250 ns noise/harmonic performance harmonic distortion hd2/hd3 f c = 100 khz, v o = 1 v p-p ?97/?100 dbc f c = 1 mhz, v o = 1 v p-p ?79/?80 dbc input voltage noise f = 100 khz 2.1 nv/hz input current noise f = 100 khz 1.4 pa/hz dc performance input offset voltage 40 300 v input offset voltage drift 1 v/c input bias current 3 5.3 a input offset current 0.1 0.5 a open-loop gain v o = 0.5 v to 2.5 v 101 123 db input characteristics input resistance, common mode 90 m input resistance, differential mode 25 k input capacitance, common mode 1 pf input capacitance, differential mode 3 pf input common-mode voltage range ?0.1 +2 v common-mode rejection ratio (cmrr) v cm = 0.4 v 86 115 db matching characteristics (ada4841-2) input offset voltage 70 v input bias current 60 na power down pin (ada4841-1) power down voltage enabled >1.6 power down voltage power down <1.2 v input current enable power down = 3 v 1 2 a power down power down = 0 v ?10 ?30 a switching speed enable 1 s power down 40 s output characteristics output voltage swing g > +1 0.045 to 2.955 0.023 to 2.988 v output current limit sourcing, v in = +v s , r l = 50 to v cm 30 ma sinking, v in = ?v s , r l = 50 to v cm 60 ma capacitive load drive 30% overshoot 30 pf power supply operating range 2.7 12 v quiescent current/amplifier power down = 3 v 1.1 1.3 ma power down = 0 v 25 60 a positive power supply rejection ratio +v s = +3 v to +4 v, ?v s = 0 v 95 110 db negative power supply rejection ratio +v s = +3 v, ?v s = 0 v to ?1 v 96 120 db
ada4841-1/ada4841-2 rev. e | page 6 of 20 absolute maximum ratings p d = quiescent power + ( total drive power ? load power ) table 4. parameter ratin supply voltage 12.6 v power dissipation see figure 5 common-mode input voltage ?v s ? 0.5 v to +v s + 0.5 v differential input voltage 1.8 v storage temperature range ?65c to +125c operating temperature range ?40c to +125c lead temperature jedec j-std-20 junction temperature 150c () l out l out s ss d r v r v v ivp 2 2 ? ? ? ? ? ? ? ? ? += rms output voltages should be considered. if r l is referenced to ?v s , as in single-supply operation, the total drive power is v s i out . if the rms signal levels are indeterminate, consider the worst case, when v out = v s /4 for r l to midsupply. () ( ) l s ss d r v ivp 2 4/ += stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in single-supply operation with r l referenced to ?v s , worst case is v out = v s /2. airflow increases heat dissipation, effectively reducing ja . in addition, more metal directly in contact with the package leads and through holes under the device reduces ja . figure 5 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8-lead soic_n (125c/w), the 6-lead sot-23 (170c/w), 8-lead msop (145c/w), and 8-lead lfcsp_wd (103c/w) on a jedec standard 4-layer board. ja values are approximations. thermal resistance ja is specified for the worst-case conditions, that is, ja is specified for device soldered in circuit board for surface-mount packages. table 5. thermal resistance 2.0 0 ?55 125 05614-061 ambient temperature (c) maximum power dissipation (w) 1.5 1.0 0.5 ?45 ?35 ?25 ?15 ?5 5 15 25 35 45 55 65 75 85 95 105 115 sot-23 soic msop lfcsp package type ja unit 8-lead soic_n 125 c/w 6-lead sot-23 170 c/w 8-lead msop 130 c/w 8-lead lfcsp_wd 103 c/w maximum power dissipation the maximum safe power dissipation for the ada4841-1/ ada4841-2 is limited by the associated rise in junction temperature (t j ) on the die. at approximately 150 c, which is the glass transition temperature, the plastic changes its properties. even temporarily exceeding this temperature limit may change the stresses that the package exerts on the die, permanently shifting the parametric performance of the amplifiers. exceeding a junction temperature of 150c for an extended period can result in changes in silicon devices, potentially causing degradation or loss of functionality. figure 5. maximum power dissipation vs. temperature for a 4-layer board esd caution the power dissipated in the package (p d ) is the sum of the quiescent power dissipation and the power dissipated in the die due to the amplifiers drive at the output. the quiescent power is the voltage between the supply pins (v s ) times the quiescent current (i s ).
ada4841-1/ada4841-2 rev. e | page 7 of 20 typical performance characteristics r l = 1 k, unless otherwise noted. 3 ?12 0.1 10 05614-021 frequency (mhz) normalized closed-loop gain (db) 1 0 ?3 ?6 ?9 v out = 2v pp v s = 5v g = +1 g = +10 g = +2 figure 6. large signal frequency response vs. gain 6 ?9 0.1 100 05614-026 frequency (mhz) closed-loop gain (db) 11 0 3 0 ?3 ?6 v in = 20mv p-p g = +1 v s = 5v 20pf with 100 snubber 0pf 10pf 20pf figure 7. small signal frequency response vs. capacitive load 3 ?12 0.1 100 05614-027 frequency (mhz) normalized closed-loop gain (db) 11 0 0 ?3 ?6 ?9 v in = 20mv p-p v s = 5v g = ?1 g = +1 g = +10 figure 8. small signal frequency response vs. gain 3 ?9 0.1 100 05614-028 frequency (mhz) gain (db) 11 0 0 ?3 ?6 v s = 5v v in = 20mv p-p g = +1 ?40c +125c +25c figure 9. small signal frequency response vs. temperature 2 ?6 0.1 100 05614-029 frequency (mhz) gain (db) 11 0 v s = +3v v s = +5v v s = 5v 1 0 ?1 ?2 ?3 ?4 ?5 v in = 20mv p-p g = +1 figure 10. small signal frequency response vs. supply voltage 3 ?9 0.1 100 05614-014 frequency (mhz) gain (db) 11 0 0 ?3 ?6 v s = 5v g = +1 2v p-p 400mv p-p 10mv p-p 20mv p-p 100mv p-p figure 11. frequency response for various v out
ada4841-1/ada4841-2 rev. e | page 8 of 20 140 ?20 10 100m 05614-042 frequency (hz) open-loop gain (db) ?40 ?160 ?60 ?80 ?100 ?120 ?140 open-loop phase (degrees) 100 1k 10k 100k 1m 10m 0 20 40 60 80 100 120 v s = 5v magnitude phase 0 ?20 figure 12. open-loop gain and phase vs. frequency ? 30 ?130 0.01 1 05614-045 frequency (mhz) harmonic distortion (dbc) 0.1 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 v s = + 5v v out = 2v p-p g = +5 second g = +2 second g = +5 third g = +2 third g = +1 third g = +1 second figure 13. harmonic distortion vs. frequency for various gains ? 30 0.01 1 05614-046 frequency (mhz) harmonic distortion (dbc) 0.1 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 v s = 5v g = +1 8v p-p third 8v p-p second 4v p-p third 4v p-p second 2v p-p third 2v p-p second figure 14. harmonic distortion vs. frequency for various output voltages ?30 ?130 0.01 1 05614-047 frequency (mhz) harmonic distortion (dbc) 0.1 ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 v out = 2v p-p g = +2 5v third +5v third 5v second +3v second +3v third +5v second figure 15. harmonic distortion vs. frequency for various supplies 10 1 10 05614-034 frequency (hz) voltage noise (nv/ hz) 100 1k 10k 100k 1m 10m v s = 5v figure 16. voltage noise vs. frequency 100 0.1 10 1m 05614-018 frequency (hz) current noise (pa/ hz) 100 1k 10k 100k 1 10 v s = 5v figure 17. current noise vs. frequency
ada4841-1/ada4841-2 rev. e | page 9 of 20 55 0 ?5 6 05614-053 offset drift distribution ( v/c) number of parts 50 45 40 35 30 25 20 15 10 5 ?4 ?2 0 2 4 count = 190 x = 0.36 v/c = 1.21 v/c figure 18. input offset voltage drift distribution 10 0 0 5 05614-013 v in (v) nonlinearity ( v) 9 8 7 6 5 4 3 2 1 1234 g = +1 v s = 5v figure 19. nonlinearity vs. v in 100 ?60 05614-036 v out (v) v offset ( v) 80 60 20 0 ?20 ?40 v s = 5 40 0 ?6 6 ?4 ?2 2 4 figure 20. input error voltage vs. output voltage 0.25 0.19 05614-033 output voltage (v) 0.24 0.23 0.22 0.21 0.20 g = +2 time = 50ns/div v s = 5v v s = +3v v s = +5v figure 21. small signal transient response for various supplies 0.15 0.09 05614-031 output voltage (v) 0.14 0.13 0.12 0.11 0.10 g = +2 v in = 20mv p-p time = 50ns/div 10pf 0pf 47pf 20pf figure 22. small signal transient response for various capacitive loads 0.130 0.090 05614-030 output voltage (v) 0.125 0.120 0.115 0.110 0.105 0.100 0.095 v s = 3v v s = 5v g = +1 time = 50ns/div figure 23. small signal transient response for various supplies
ada4841-1/ada4841-2 rev. e | page 10 of 20 6 ?1 05614-019 input and output voltage (v) 5 4 3 2 1 0 v s = 5v g = +1 time = 200ns/div v in v out figure 24. input overdrive recovery 6 ?1 05614-023 input and output voltage (v) 5 4 3 2 0 v s = 5v g = +2 time = 100ns/div 1 v in 2 v out figure 25. output overdrive recovery 1.5 ?1.5 05614-022 output voltage (v) 1.0 0.5 0 ?0.5 ?1.0 v s = 5v v out = 2v p-p time = 100ns/div g = +2 g = +1 figure 26. large signal transient response for various gains 4.5 0 05614-016 output voltage (v) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 g = +2 v s = 5 time = 100ns/div +25c ?40c +125c figure 27. slew rate vs. temperature 2.0 ?2.0 05614-041 expanded v out (mv) v in and v out (v) 2.0 ?2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 v s = 5v g = +1 v out = 2v p-p time = 100ns/div v out v in v out (expanded) figure 28. settling time 6 ?1 05614-039 power down pin (v) 5 4 3 2 1 0 v s = 5v g = +1 v in = 1v dc time = 200ns/div 1.2 ?0.2 1.0 0.8 0.6 0.4 0.2 0 v out (v) power down pin ?40c +25c +125c figure 29. power-up time vs. temperature
ada4841-1/ada4841-2 rev. e | page 11 of 20 6 ?1 05614-040 power down pin (v) 5 4 3 2 1 0 v s = 5v g = +1 v in = 1v dc time = 10 s/div 1.2 ?0.2 1.0 0.8 0.6 0.4 0.2 0 v out (v) +125c +25c ?40c power down pin power down pin figure 30. power down time vs. temperature 1.6 ?0.2 05 05614-020 power down pin (v) supply current/amplifier (ma) . 0 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v s = 5v +25c ?40c +125c figure 31. supply current per amplifier vs. power down pin voltage 0 ?120 100 100m 05614-009 frequency (hz) common-mode rejection (db) 1k 10k 100k 1m 10m ?20 ?40 ?60 ?80 ?100 v s = 5v g = +1 figure 32. cmr vs. frequency 0 ?120 100 100m 05614-025 frequency (hz) power supply re jection (db) 1k 10k 100k 1m 10m ?20 ?40 ?60 ?80 ?100 v s = 5v +psr ?psr figure 33. psr vs. frequency 100 0.001 100 100m 05614-024 frequency (hz) closed-loop output impedance ( ) 1k 10k 100k 1m 10m 10 1 0.1 0.01 v s = 5v figure 34. output im pedance vs. frequency 40 ?50 ?40 125 05614-057 temperature (c) input offset voltage ( v) 30 20 10 0 ?10 ?20 ?30 ?40 ?25?105 203550658095110 v s = +5v v s = 5v v s = +3v figure 35. input offset voltage vs. temperature for various supplies
ada4841-1/ada4841-2 rev. e | page 12 of 20 atob btoa g=+1 v s =5v r l =1k ? frequency (hz) crosstalk (db) ? 40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 ?140 10k 100k 1m 10m 1g 100m 05614-062 3.6 3.1 ?40 125 05614-058 temperature (c) input bias current ( p a) ?25?105 203550658095110 3.5 3.4 3.3 3.2 v s = +3v v s = +5v v s = 5v figure 36. input bias current vs. temperature for various supplies figure 38. crosstalk output to output 1.6 0.8 ?40 125 05614-059 temperature (c) supply current (ma) ?25?105 203550658095110 v s = +5v v s = 5v v s = +3v 1.5 1.4 1.3 1.2 1.1 1.0 0.9 figure 37. supply current vs. temperature for various supplies
ada4841-1/ada4841-2 rev. e | page 13 of 20 theory of operation amplifier description the ada4841-1/ada4841-2 are low power, low noise, precision voltage-feedback op amps for single or dual voltage supply operation. the ada4841-1/ada4841-2 are fabricated on adis second generation xfcb process and feature trimmed supply current and offset voltage. the 2.1 nv/hz voltage noise (very low for a 1.1 ma supply current amplifier), 40 v offset voltage, and sub 1 v/c offset drift is accomplished with an input stage made of an undegenerated pnp input pair driving a symmetrical folded cascode. a rail-to-rail output stage provides the maximum linear signal range possible on low voltage supplies and has the current drive capability needed for the relatively low resistance feedback networks required for low noise operation. cmrr, psrr, and open-loop gain are all typically above 100 db, preserving the precision performance in a variety of configurations. gain bandwidth is kept high for this power level to preserve the outstanding linearity performance for frequencies up to 100 khz. the ada4841-1 has a power- down function to further reduce power consumption. all this results in a low noise, power efficient, precision amplifier that is well-suited for high resolution and precision applications. dc errors figure 39 shows a typical connection diagram and the major dc error sources. the ideal transfer function (all error sources set to 0 and infinite dc gain) can be written as in g f ip g f out v r r v r r v ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? += 1 (1) 05614-004 r g ? v in + r s ? v ip + i b + i b ? + v out ? r f + v os ? figure 39. typical connection diagram and dc error sources this reduces to the familiar forms for inverting and noninverting op amp gain expressions ip g f out v r r v ? ? ? ? ? ? ? ? += 1 (2) (noninverting gain, v in = 0 v) in g f out v r r v ? ? ? ? ? ? ? ? ? = (3) (inverting gain, v ip = 0 v) the total output voltage error is the sum of errors due to the amplifier offset voltage and input currents. the output error due to the offset voltage can be estimated as ? ? ? ? ? ? ? ? + ? ? ? ? ? ? + ? ++ = g f out pnom p offset out r r a v psrr vv cmrr vcm v v nom error 1 (4) where: nom offset v is the offset voltage at the specified supply voltage. this is measured with the input and output at midsupply. vcm is the common-mode voltage. v p is the power supply voltage. nom p v is the specified power supply voltage. cmrr is the common-mode rejection ratio. psrr is the power supply rejection ratio. a is the dc open-loop gain. the output error due to the input currents can be estimated as + ? ? ? ? ? ? ? ? ? +? ? ? ? ? ? ? ? ? + = b g f s b g f g f out i r r ri r r rr v error 1 1)||( (5) note that setting r s equal to r f ||r g compensates for the voltage error due to the input bias current. noise considerations figure 40 illustrates the primary noise contributors for the typical gain configurations. the total rms output noise is the root-mean-square of all the contributions. 0 5614-005 r g r s ien ien + vout_en ? r f ven 4kt r s vn _ r s = 4kt r g vn _ r g = 4kt r f vn _ r f = figure 40. noise sources in typical connection
ada4841-1/ada4841-2 rev. e | page 14 of 20 the output noise spectral density can be calculated by [] 2 2 2 2 2 2 2 4 414 f g f s g f rienktrg r r venrienktrs r r ktrf envout + ? ? ? ? ? ? ? ? +++ ? ? ? ? ? ? ? ? ++ = _ (6) where: k is boltzmanns constant. t is the absolute temperature, degrees kelvin. ien is the amplifier input current noise spectral density, pa/hz. ven is the amplifier input voltage spectral density, nv/hz. r s is the source resistance as shown in figure 40 . r f and r g are the feedback network resistances, as shown in figure 40 . source resistance noise, amplifier voltage noise ( ven ), and the voltage noise from the amplifier current noise ( ien r s ) are all subject to the noise gain term (1 + r f /r g ). note that with a 2.1 nv/hz input voltage noise and 1.4 pa/hz input current, the noise contributions of the amplifier are relatively small for source resistances between approximately 200 and 30 k. shows the total rti noise due to the amplifier vs. the source resistance. in addition, the value of the feedback resistors used impacts the noise. it is recommended to keep the value of feedback resistors between 250 and 1 k to keep the total noise low. figure 41 1000 0.1 10 100k 05614-007 source resistance ( ) noise (nv/ hz) 100 10 1 100 1k 10k total amplifier noise source resistance noise amplifier + resistor noise figure 41. rti noise vs. source resistance headroom considerations the ada4841-1/ada4841-2 are designed to provide maximum input and output signal ranges with 16-bit to 18-bit dc linearity. as the input or output headroom limits are reached, the signal linearity degrades. the input stage positive limit is almost exactly a volt below the positive supply at room temperature. input voltages above that start to show clipping behavior. the positive input voltage limit increases with temperature with a coefficient of about 2 mv/c. the lower supply limit is nominally below the minus supply; therefore, in a standard gain configuration, the output stage limits the signal headroom on the negative supply side. figure 42 and figure 43 show the nominal cmrr behavior at the limits of the input headroom for three temperaturesthis is generated using the subtractor topology shown in figure 44 , which avoids the output stage limitation. 300 ?300 3.00 5.00 05614-055 common-mode voltage (v) common-mode error ( v) 260 220 180 140 100 60 20 ?20 ?60 ?100 ?140 ?180 ?220 ?260 3.20 3.40 3.60 3.80 4.00 4.20 4.40 4.60 4.80 ?40c +25c +125c figure 42. +cmv vs. common-mode error vs. v os 0 ?800 ?6.00 ?4.00 05614-054 common-mode voltage (v) common-mode error ( v) ?50 ?100 ?150 ?200 ?250 ?300 ?350 ?400 ?450 ?500 ?550 ?600 ?650 ?700 ?750 ?5.80 ?5.60 ?5.40 ?5.20 ?5.00 ?4.80 ?4.60 ?4.40 ?4.20 ?40c +25c +125c figure 43. ?cmv vs. common-mode error vs. v os + v out ? ? v cm + 05614-051 figure 44. common-range subtractor
ada4841-1/ada4841-2 rev. e | page 15 of 20 figure 45 shows the amplifier frequency response as a g = ?1 inverter with the input and output stage biased near the negative supply rail. 6 ?12 0.1 100 05614-017 frequency (mhz) gain (db) 11 0 3 0 ?3 ?6 ?9 v s+ = 5v g = ?1 v in = 20mv p-p v s? = ?50mv v s? = ?100mv v s? = ?200mv v s? = ?20mv v s? = ?150mv figure 45. small signal frequency response vs. negative supply bias the input voltage (v in ) and reference voltage (v ip ) are both at 0 v, (see figure 39 ). +v s is biased at +5 v, and ?v s is swept from ?200 mv to ?20 mv. with the input and output voltages biased 200 mv above the bottom rail, the g = ?1 inverter frequency response is not much different from what is seen with the input and output voltages biased near midsupply. at 150 mv bias, the frequency response starts to decrease and at 20 mv, the inverter bandwidth is less than half its nominal value. capacitance drive capacitance at the output of an amplifier creates a delay within the feedback path that, if within the bandwidth of the loop, can create excessive ringing and oscillation. the g = +1 follower topology has the highest loop bandwidth of any typical configuration and, therefore, is the most vulnerable to the effects of capacitance load. a small resistor in series with the amplifier output and the capacitive load mitigates the problem. figure 46 plots the recommended series resistance vs. capacitance for gains of +1, +2, and +5. 60 0 10 10000 05614-050 capacitance load (pf) series resistance ( ) 50 40 30 20 10 100 1000 g = +1 g = +2 g = +5 figure 46. series resistance vs. capacitance load input protection the ada4841-1/ada4841-2 are fully protected from esd events, withstanding human body model esd events of 2.5 kev and charge device model events of 1 kev with no measured performance degradation. the precision input is protected with an esd network between the power supplies and diode clamps across the input device pair, as shown in figure 47 . 05614-006 vp esd esd vee vcc bias to rest of amplifier vn esd esd figure 47. input stage and protection diodes for differential voltages above approximately 1.4 v, the diode clamps start to conduct. too much current can cause damage due to excessive heating. if large differential voltages need to be sustained across the input terminals, it is recommended that the current through the input clamps be limited to below 150 ma. series input resistors sized appropriately for the expected differential overvoltage provide the needed protection. the esd clamps start to conduct for input voltages more than 0.7 v above the positive supply and input voltages more than 0.7 v below the negative supply. it is recommended that the fault current be limited to less than 150 ma if an overvoltage condition is expected.
ada4841-1/ada4841-2 rev. e | page 16 of 20 the power down pin is protected with esd clamps, as shown in . voltages beyond the power supplies cause these diodes to conduct. the guidelines for limiting the overload current in the input protection section should also be followed for the figure 48 power down pin. power-down operation figure 48 shows the ada4841-1 power-down circuitry. if the power down pin is left unconnected, then the base of the input pnp transistor is pulled high through the internal pull-up resistor to the positive supply, and the part is turned on. pulling the power down pin approximately 1.7 v below the positive supply turns the part off, reducing the supply current to approximately 40 a. 05614-052 vcc vee power down esd esd i bias to amplifier bias figure 48. power down circuit
ada4841-1/ada4841-2 rev. e | page 17 of 20 applications information typical performance values to reduce design time and eliminate uncertainty table 6 provides a convenient reference for typical gains, component values, and performance parameters. 16-bit adc driver the combination of low noise, low power, and high speed make the ada4841-1/ada4841-2 the perfect driver solution for low power, 16-bit adcs, such as the ad7685 . figure 50 shows a typical 16-bit single-supply application. there are different challenges to a single-supply, high resolution design, and the ada4841-1/ada4841-2 address these nicely. in a single-supply system, a main challenge is using the amplifier in buffer mode with the lowest output noise and preserving linearity compatible with the adc. rail-to-rail input amplifiers are usually higher noise than the ada4841-1/ada4841-2 and cannot be used in this mode because of the nonlinear region around the crossover point of their input stages. the ada4841-1/ada4841-2, which have no crossover region but have a wide linear input range from 100 mv below ground to 1 v below positive rail, solve this problem, as shown in figure 50 . the amplifier, when configured as a follower, has a linear signal range from 0.25 v above the minus supply voltage (limited by the amplifiers output stage) to 1 v below the positive supply (limited by the amplifier input stage). a 0 v to +4.096 v signal range can be accommodated with a positive supply as low as +5.2 v and a negative power supply of ?0.25 v. the 5.2 v supply also allows the use of a small, low dropout, low temperature drift adr364 reference voltage. if ground is used as the amplifier negative supply, then note that at the low end of the input range close to ground, the ada4841-1/ ada4841-2 exhibit substantial nonlinearity, as any rail-to-rail output amplifier. the ada4841-1/ada4841-2 drive a one- pole, low-pass filter. this filter limits the already very low noise contribution from the amplifier to the ad7685. reconstruction filter the ada4841-1/ada4841-2 can also be used as a reconstruction filter at the output of dacs for suppression of the sampling frequency. the filter shown in figure 49 is a two-pole, 500 khz sallen-key lpf with a fixed gain of g = +1.6. u1 c2 1320pf r3 840 input +5v 10 f 0.1 f ?5v 10 f 0.1 f output 05614-044 c1 1320pf r2 249 r1 249 r4 499 figure 49. two-pole 500 khz reconstruction filter schematic setting the resistors and capacitors equal to each other greatly simplifies the design equations for the sallen-key filter. the corner frequency, or ?3 db frequency, can be described by the equation 112 1 c r f c = the quality factor, or q , is shown in the equation k q ? = 3 1 for minimum peaking, set q equal to 0.707. the gain, or k, of the amplifier is 1 += resistor values are kept low for minimal noise contribution, offset voltage, and optimal frequency response. ad7685 ref gnd vdd in? in+ vio sdi sck sdo cnv 100nf 10 f adr364 33 2.7nf ?0.25v 0v to 4.096v ada4841 100nf +5.2v 100nf 05614-060 figure 50. adc driver schematic
ada4841-1/ada4841-2 rev. e | page 18 of 20 table 6. recommended values and typical performance gain r f () r g () ?3 db bw (mhz) slew rate (v/s) peaking (db) output noise ada4841-1/ ada4841-2 only (nv/hz) total output noise including resistors (nv/hz) +1 0 n/a 77 12.5 0.9 2 2 +2 499 499 34 12.5 0.3 4 5.73 ?1 499 499 38 12.5 0.4 4 5.73 +5 499 124 11 12 0 10 11.9 +10 499 54.9 5 12 0 20 21.1 +20 499 26.1 2.3 11.2 0 40 42.2 capacitor selection is critical for optimal filter performance. capacitors with low temperature coefficients, such as npo ceramic capacitors, are good choices for filter elements. figure 51 shows the filter response. 05614-043 0.03 10 frequency (mhz) 1 0.1 ?40 gain (db) ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 5 figure 51. filter frequency response layout considerations to ensure optimal performance, careful and deliberate attention must be paid to the board layout, signal routing, power supply bypassing, and grounding. ground plane it is important to avoid ground in the areas under and around the input and output of the ada4841-1/ada4841-2. stray capacitance created between the ground plane and the input and output pads of a device are detrimental to high speed amplifier performance. stray capacitance at the inverting input, along with the amplifier input capacitance, lowers the phase margin and can cause instability. stray capacitance at the output creates a pole in the feedback loop. this can reduce phase margin and can cause the circuit to become unstable. power supply bypassing power supply bypassing is a critical aspect in the performance of the ada4841-1/ada4841-2. a parallel connection of capacitors from each of the power supply pins to ground works best. a typical connection is shown in figure 49 . smaller value capacitors offer better high frequency response where larger value electrolytics offer better low frequency performance. paralleling different values and sizes of capacitors helps to ensure that the power supply pins are provided a low ac impedance across a wide band of frequencies. this is important for minimizing the coupling of noise into the amplifier. this can be especially important when the amplifier psr is starting to roll offthe bypass capacitors can help lessen the degradation in psr performance. starting directly at the ada4841-1/ada4841-2 power supply pins, the smallest value capacitor should be placed on the same side of the board as the amplifier, and as close as possible to the amplifier power supply pin. the ground end of the capacitor should be connected directly to the ground plane. keeping the capacitors distance short but equal from the load is important and can improve distortion performance. this process should be repeated for the next largest value capacitor. it is recommended that a 0.1 f ceramic 0508 case be used. the 0508 case size offers low series inductance and excellent high frequency performance. a 10 f electrolytic capacitor should be placed in parallel with the 0.1 f capacitor. depending on the circuit parameters, some enhancement to performance can be realized by adding additional capacitors. each circuit is different and should be individually analyzed for optimal performance.
ada4841-1/ada4841-2 rev. e | page 19 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 52. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) compliant to jedec standards mo-187-aa 6 0 0.80 0.55 0.40 4 8 1 5 0.65 bsc 0.40 0.25 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.09 3.20 3.00 2.80 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 10-07-2009-b figure 53. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters compliant to jedec standards mo-178-ab 121608-a 10 4 0 seating plane 1.90 bsc 0.95 bsc 0.60 bsc 65 123 4 3.00 2.90 2.80 3.00 2.80 2.60 1.70 1.60 1.50 1.30 1.15 0.90 0 .15 max 0 .05 min 1.45 max 0.95 min 0.20 max 0.08 min 0.50 max 0.30 min 0.55 0.45 0.35 pin 1 indicator figure 54. 6-lead small outline transistor package [sot-23] (rj-6) dimensions shown in millimeters
ada4841-1/ada4841-2 rev. e | page 20 of 20 2.54 2.44 2.34 111809-a top view 8 1 5 4 0.30 0.25 0.20 bottom view pin 1 index area seating plane 0.80 0.75 0.70 1.80 1.70 1.60 0.203 ref 0.05 max 0.02 nom 0.50 bsc exposed pad 3.10 3.00 sq 2.90 p i n 1 i n d i c a t o r ( r 0 . 1 5 ) forproperconnectionof the exposed pad, refer to the pin configuration of this data sheet. coplanarity 0.08 0.50 0.40 0.30 compliant to jedec standards mo-229-weed figure 55. 8-lead lead frame chip scale package [lfcsp_wd] 3 mm 3 mm body, very very thin, dual lead (cp-8-11) dimensions shown in millimeters ordering guide model 1 temperature range package description pack age option ordering quantity branding ada4841-1yrz ?40c to +125c 8-lead soic_n r-8 1 ada4841-1yrz-r7 ?40c to +125c 8-lead soic_n r-8 1,000 ada4841-1yrz-rl ?40c to +125c 8-lead soic_n r-8 2,500 ada4841-1yrjz-r2 ?40c to +125c 6-lead sot-23 rj-6 250 hqb ada4841-1yrjz-r7 ?40c to +125c 6-lead sot-23 rj-6 3,000 hqb ada4841-1yrjz-rl ?40c to +125c 6-lead sot-23 rj-6 10,000 hqb ada4841-2yrmz ?40c to +125c 8-lead msop rm-8 1 hrb ada4841-2yrmz-r7 ?40c to +125c 8-lead msop rm-8 1,000 hrb ada4841-2yrmz-rl ?40c to +125c 8-lead msop rm-8 3,000 hrb ada4841-2yrz ?40c to +125c 8-lead soic_n r-8 1 ada4841-2yrz-r7 ?40c to +125c 8-lead soic_n r-8 1,000 ada4841-2yrz-rl ?40c to +125c 8-lead soic_n r-8 2,500 ada4841-2ycpz-r2 ?40c to +125c 8-lead lfcsp_wd cp-8-11 250 hrb ada4841-2ycpz-r7 ?40c to +125c 8-lead lfcsp_wd cp-8-11 1,500 hrb ada4841-2ycpz-rl ?40c to +125c 8-lead lfcsp_wd cp-8-11 5,000 hrb ada4841-1yr-ebz ?40c to +125 c evaluation board ada4841-1yrj-ebz ?40c to + 125c evaluation board ada4841-2yrm-ebz ?40c to +125c evaluation board ada4841-2yr-ebz ?40c to +125 c evaluation board 1 z = rohs compliant part. ?2005C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d05614C0C12/10(e)

▲Up To Search▲

Price & Availability of MODEL1

	To Download MODEL1 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .